Energy-Delay Space Exploration of Clocked Storage Elements Using Circuit Sizing
نویسندگان
چکیده
Rapid energy-delay exploration methodology based on circuit sizing as applied to clocked storage elements is presented. Circuit delay and energy are modeled using improved RC delay model of a transistor. The accuracy of the model is increased by using Logical Effort setup accounting for input signal slope and extraction of technology dependent parameters. The minimal energy-delay curve is generated by optimizing transistor sizes for minimum energy at given delay targets. Results show two orders of magnitude time improvement as compared to H-SPICE in order to generate such curves while the delay accuracy of the model used remains within 10 % as compared to H-SPICE.
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